CORE-ET is the open-sourced CPU subsystem behind the Erbium SoC: eight dual-threaded RV64IMFC ET-Minion cores, each fused to an 8-lane vector unit built for tensor math, sharing an instruction cache, a barrier fabric, and a 512-bit ET-Link into the memory hierarchy. Every block on this page comes straight from the microarchitecture specifications in the repository.
The floorplan below follows the physical layout in the Neighborhood MAS: two columns of four Minions flank a central channel of shared logic, and every port exits north into the Shire. Select any block to read its role.
Each Minion is a dual-threaded, in-order, single-issue RV64IMFC core (M · F · C · Zicsr · Zifencei) split into four blocks: a Frontend that fetches from the shared ICache, an integer pipeline, a private 4 KB DCache that doubles as scratchpad, and the Vector Processing Unit.
An 8-stage frontend with one instruction-stream buffer per thread (2 × 32 B entries), fetching over the pipelined ICache interface. The VPU decoder lives in Frontend stage 5 so timing-clean control signals arrive at the vector unit.
An in-order integer pipeline with a MulDiv unit, CSR file, and three scoreboards (INT, FP, mask) tracking dependencies against the VPU. A dedicated GSC stage iterates gather/scatter addresses lane by lane.
A private data cache wide enough to fill one register-file entry across all 8 VPU lanes in a single cycle. Two hardware FSMs run TensorLoads: one fills the L1 scratchpad, one streams operands straight into the VPU.
Eight identical lanes running in lockstep behind a control unit with its own µ-instruction sequencers. To software it is a single machine executing eight operations per cycle over 256-bit registers, masked per lane by M0.
64 × 32-bit registers per lane (32 per thread). Seen across lanes: thirty-two 256-bit vector registers, viewable as 8×32b, 16×16b, or 32×8b objects.
Tensor fused multiply-add: one FP32 or two FP16 multiply-adds per cycle, feeding TensorFMA and TensorQuant operations.
Two INT8 tensor multiply-accumulate units per lane — 16 INT8 MACs per core per cycle for quantized inference.
32-bit integer/logic unit with short-swizzle support for packed-integer instructions.
ROM-backed transcendentals — exp2, log2, reciprocal — sequenced as µ-instructions by the VPU control.
Full bypass network at each lane's unit inputs to collapse operand dependencies without stalling.
Data moves over ET-Link — a two-channel valid/ready protocol carrying up to one 64-byte cache line per cycle per direction — into a Shire Cache whose SRAM is partitioned at boot into private L2, a distributed slice of the global L3, and software-managed scratchpad. Coherence is deliberately absent: software owns it, hardware spends the power budget on math.
Private, VPU-width fills, TensorLoad FSMs bypass into scratchpad.
1 RF entry × 8 lanes / cycleTwo 16-entry fully-associative L0s (one per 4 Minions) in front of a shared L1 ICache.
fixed-latency L0 hit pathRequest + reply channels, valid/ready handshake through arbiters, crossbars, and FIFOs.
512 b / cycle / channel4 banks, 4-way, 64 B lines, write-back/write-allocate, full SECDED ECC on tag, state, and data.
4 MB POR · non-coherentL3 and scratchpad slivers distributed across Shires; writeAround coalescing preserves mesh bandwidth.
To_L3 / To_Sys · 512 bInference kernels tile across cores. CORE-ET makes the coordination cost close to free with dedicated hardware in each Neighborhood and CPU subsystem, driven directly from CSR writes.
User-mode barrier counters atomically incremented from a CSR write — all eight Minions rendezvous without a trip through memory.
Producer/consumer flow control in hardware: consumers block (or poll, non-blocking) on credits that producers grant through CREDINC registers.
When many Minions stream the same tensor, their L2 read requests are coalesced into one — same data, one transaction's worth of power and bandwidth. A TensorStore twin handles the write side.
A dedicated Minion-to-Minion messaging network, routed for minimal wirelength across the two Minion columns.
A 64-bit CLINT timer plus inter-processor software interrupts at the CPU-subsystem level.
A standard RISC-V Platform-Level Interrupt Controller routes external interrupts to all sixteen hardware threads.
| Parameter | Value | Source |
|---|---|---|
| ISA | RV64IMFC + Zicsr + Zifencei, M/S privilege (trap-and-emulate deviations documented) | Minion Description |
| Core µarch | Dual-threaded, in-order, single-issue; FE + Intpipe + DCache + VPU | Minion Description |
| Vector state | 32 × 256-bit registers; 8 × 8-bit mask registers; per-lane M0 predication | VPU Specification / ET PRM |
| Tensor math | TXFMA (1×FP32 or 2×FP16 FMA/lane) + 2× TIMA INT8 MAC/lane; TensorFMA, TensorQuant, TensorStore/Reduce sequencers | VPU Specification |
| Transcendentals | exp2, log2, reciprocal via per-lane ROM-backed unit | VPU Specification |
| L1 DCache | 4 KB private per core, scratchpad-capable, dual TensorLoad FSMs | Minion DCache Description |
| ICache | 2 × L0 µcache (16-entry fully associative, 4 Minions each) + 32 KB shared L1 | Neighborhood ICache / FE–ICache Interface |
| Neighborhood | 8 Minions, 2 PTWs, Coop TLoad/TStore, FLMN, FLB, FCC, PMU, ESRs; LV/HV clock & voltage domains with DLL-derived Neighborhood clock | Neighborhood MAS / Shire DLL docs |
| ET-Link | Request + reply channels, 512 b (64 B line) per cycle each, valid/ready handshake | ET-Link Specification |
| Shire Cache | 4 banks (build-time 4/8), 1–8 MB SRAM (POR 4 MB), boot-time L2/L3/SCP partitioning, 4-way, 64 B lines, WB/WA, SECDED ECC, writeAround coalescing, non-coherent | Shire Cache Specification |
| Subsystem | 1 Neighborhood + external L1 I$ SRAM + PLIC + CLINT (10 MHz) + FLB/FCC + CPU registers; AXI4 initiator of the Erbium SoC | Repository README |